Simple GNU Make File

GNU Make contains many default rules, referred to as implicit rules, to simplify the construction of makefiles. For example, these specify that ‘.o’ files can be obtained from ‘.c’ files by compilation, and that an executable can be made by linking together ‘.o’ files. Implicit rules are defined in terms of make variables, such as CC (the C compiler) and CFLAGS (the compilation options for C programs), which can be set using VARIABLE=VALUE lines in the makefile.

A simple ‘Makefile’ for the project above can be written as follows:

CC=gcc
CFLAGS=-Wall
main: main.o hai.o hello.o
clean:
rm -f main main.o hello.o hai.o

The meaning of make file is like :
1) Using the C compiler gcc, with compilation option -Wall,
2)Build the target executable main from the object files ‘main.o’ ,‘hello.o and’hai.o'
3)These, in turn, will be built from ‘main.c’ ,'hai.c'and ‘hello.c’.
4)The target clean has no dependencies and simply removes all the compiled files.
The option -f (force) on the rm command suppresses any error messages if the files do not exist.
To use the makefile, simply type make.
 When called with no arguments, the first target in the makefile is built, producing the executable ‘main’:
To remove the generated files, type make clean:

Another example of make file:

CC = gcc
CFLAGS = -g -W -Wall
OBJ = main.o hai.o hello.o
.c.o:
$(CC) $(CFLAGS) $<

all: $(OBJ)

clean:

rm -f *.o

Linux Makefile

COPY FROM: http://forum.codecall.net ->linux-tutorials-guides-tips->17681-linux-makefile-tutorial

Introduction

The make program essentially is used to update targets (exe or object files) according to the dependency instructions, typically present in a file called makefile. The program automatically can link dependent modules and also decide which files are to be (re)compiled by looking at the object code timestamps. Essentially make allows the compilation process to be a breeze.

Makefile Description

The makefile contains all the dependency information required for compiling. The file is typically denoted as makefile or Makefile. This however can be overridden by specifying the file name with the -f switch. The instructions are written in single lines and interpreted accordingly. A backslash (\) can be used to signify continuation of the line.

The target is the final output that is required at the end of the make process. It typically is reliant on many other files to have compiled successfully. Target compilation are carried out by a series of actions called as command. Rule can be composed of multiple commands but each starting with a tab character.

Makefile has the feature of using variables, like in other programming languages. A variable is defined as:

variable_name = variable_definition

$(variable_name) is used to use its value.

Make software also has set of internal macros:

$+

List of all the defined dependencies, space separated, with duplicates

$^

List of all the defined dependencies, space separated, without duplicates

$@

Contains the name of the current target

$<

Current prerequisite modified later than the current target  ie..  the name of the related file that caused the action.

$* 
the prefix shared by target and dependent files. 

Make Options

The makefile typically has the contents are specified below:

Empty Lines

Lines with no text are ignored

#

Pound acts as a start of comments (single-line) indicator

Dependencies

targets: dependency; commands

Here the targets and their dependencies are specified. If the dependent files have not been created or a newer version of their source code exists, then the files are regenerated. These can be followed by one or more commands. If there are no dependencies then the commands are executed always.

Make Options

-f makefile

The specified makefile is used as the description file

-h

Print the help information

-i

Ignore any errors

-n

Prints the command that will be executed. For testing the flow of the compilation process.

-q

Returns 0 if the target file is up to date; non-zero if otherwise

-p

Prints out the variables and settings existing by default

Running Make

Now to put all the above options to use. We will build a descriptor file to build an exe called sampleexec. Also assume that it needs two source files src1.c and src2.c. To build a descriptor for this and save it in a file called makefile.

The makefile will look like this

Code:

     sampleexec : src1.o src2.o 

             gcc -o sampleexec src1.o src2.o

     src1.o : src1.c 

             gcc -c src1.c

     src2.o : src2.c 

             gcc -c src2.c

To compile just run:

Code:

# make

Steps make takes to compile sampleexec:

sees that sampleexec depends on the object files src1.o src2.o

looks for the target definition of the two object files.

sees that src1.o depends on the file src1.c

executes the commands given in src1.o's rule and compiles src1.c to get the object file.

similarly looks at the target src2.o and compiles the object files

prepares sampleexc by combining the two object files


Common implicit rule is for the construction of .o (object) files out of .cpp (source files):


.o.cpp:
        $(CC) $(CFLAGS) -c $<
alternatively
.o.cpp:
        $(CC) $(CFLAGS) -c $*.c