Simple GNU Make File

GNU Make contains many default rules, referred to as implicit rules, to simplify the construction of makefiles. For example, these specify that ‘.o’ files can be obtained from ‘.c’ files by compilation, and that an executable can be made by linking together ‘.o’ files. Implicit rules are defined in terms of make variables, such as CC (the C compiler) and CFLAGS (the compilation options for C programs), which can be set using VARIABLE=VALUE lines in the makefile.

A simple ‘Makefile’ for the project above can be written as follows:

CC=gcc
CFLAGS=-Wall
main: main.o hai.o hello.o
clean:
rm -f main main.o hello.o hai.o

The meaning of make file is like :
1) Using the C compiler gcc, with compilation option -Wall,
2)Build the target executable main from the object files ‘main.o’ ,‘hello.o and’hai.o'
3)These, in turn, will be built from ‘main.c’ ,'hai.c'and ‘hello.c’.
4)The target clean has no dependencies and simply removes all the compiled files.
The option -f (force) on the rm command suppresses any error messages if the files do not exist.
To use the makefile, simply type make.
 When called with no arguments, the first target in the makefile is built, producing the executable ‘main’:
To remove the generated files, type make clean:

Another example of make file:

CC = gcc
CFLAGS = -g -W -Wall
OBJ = main.o hai.o hello.o
.c.o:
$(CC) $(CFLAGS) $<

all: $(OBJ)

clean:

rm -f *.o